The invention relates generally to integrated circuits with thin device areas and more specifically to an improved method of making ultra-thin wafers.
The formation of thin device areas is generally produced in the prior art by epitaxially depositing the device area on a substrate, applying a handling wafer to the epitaxially layer and then removing the original substrate. The ultimate wafer includes the thickness of the handle as well as the epitaxial layer. The epitaxial layer is generally in the range of 5 to 25 microns and the handle is in the range of 19 to 24 mils. The processing to remove the original substrate affects the quality of the surface of the epitaxial layer in which the devices are to be formed. Also the planarity of the surface may be affected. In some applications, as shown in U.S. Pat. No. 4,292,730, the epitaxial layer may have other layers and handles applied thereto and the original handle removed. In this specific patent, both surfaces of the epitaxial layer have been treated in the process and thereby increase possible quality control of the device surfaces as well as planarity.
Thus, it is an object of the present invention to provide a method of fabricating ultra-thin wafers without modification of the surface of the device layer in which devices are to be formed.
Another object of the present invention is to provide a method of fabricating ultra-thin wafers in a thickness not greater than 7 mils.
These and other objects are obtained by bonding a first device wafer to a handle wafer by an intermediate oxide layer and thinning the first device wafer to not greater than 7 mils in thickness above the oxide layer. Device formation steps are performed in an epitaxial layer deposited on the first device wafer. This is followed by removing the handle wafer with an etch which stops on the intermediate oxide layer to produce a resulting wafer having substantially the thickness of the first wafer. In addition to the device forming steps, device isolation steps are also performed between the bonding and the removing of the handle steps. To produce a silicon on insulator (SOI), the handle wafer and first device wafer (not greater than 7 mils thick) is oxidized to form an intermediate oxide layer and a third device wafer is then bonded to the surface of the first device wafer. This intermediate oxide layer forms part of the isolation layer of the resulting wafer after removal of the handle wafer. The device formation steps are then formed in the surface of the third device wafer. Lateral isolation can then be formed by introducing impurities for lateral junction isolation or the third device wafer can be etched to form lateral dielectric isolation by air or by filling with dielectric material. Alternatively, oxygen implantation may be performed on the first device wafer to produce the horizontal dielectric oxide layer. Any of the isolation techniques may also be performed on the first device wafer without the use of a third device wafer. The handle wafer is removed by grinding a substantial portion of the thickness of the handle wafer and etching the remaining portion of the handle wafer using the first bonding oxide layer as an etching stop.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.